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NTTFS4840N Power MOSFET
Features
30 V, 26 A, Single N-Channel, m8FL
* * * * * * * * *
Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant DC-DC Converters Point of Load Power Load Switch Notebook Battery Management Motor Control
Parameter Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current RqJA (Note 1) Power Dissipation RqJA (Note 1) Continuous Drain Current RqJA 10 s (Note 1) Power Dissipation RqJA 10 s (Note 1) Continuous Drain Current RqJA (Note 2) Power Dissipation RqJA (Note 2) Continuous Drain Current RqJC (Note 1) Power Dissipation RqJC (Note 1) Pulsed Drain Current Current Limited by Pkg. Steady State TA = 25C TA = 85C TA = 25C TA = 25C TA = 85C TA = 25C TA = 25C TA = 85C TA = 25C TC = 25C TC = 85C TC = 25C TA = 25C, tp = 10 ms TA = 25C PD IDM IDmaxPkg TJ, Tstg IS dV/dt EAS PD ID PD ID PD ID Symbol VDSS VGS ID Value 30 20 7.3 5.3 2.2 10.3 7.5 4.4 4.6 3.3 0.84 26 19 27.8 77 20 -55 to +150 23 6.0 16.7 W A A C A V/ns mJ W A W A 4840 A Y WW G = Specific Device Code = Assembly Location = Year = Work Week = Pb-Free Package W A
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V(BR)DSS 30 V RDS(on) MAX 24 mW @ 10 V 36 mW @ 4.5 V ID MAX 26 A
Applications
N-Channel MOSFET D (5-8) Unit V V A S (1,2,3) G (4)
MAXIMUM RATINGS (TJ = 25C unless otherwise stated)
MARKING DIAGRAM
WDFN8 (m8FL) CASE 511AB 1 S S S G 4840 AYWWG G D D D D
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device NTTFS4840NTAG NTTFS4840NTWG Package Shipping WDFN8 1500/Tape & Reel (Pb-Free) WDFN8 5000/Tape & Reel (Pb-Free)
Operating Junction and Storage Temperature Source Current (Body Diode) Drain to Source DV/DT Single Pulse Drain-to-Source Avalanche Energy (TJ = 25C, VDD = 50 V, VGS = 10 V, IL = 18.3 Apk, L = 0.1 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8 from case for 10 s)
TL
260
C
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface-mounted on FR4 board using 1 sq-in pad, 1 oz Cu. 2. Surface-mounted on FR4 board using the minimum recommended pad size.
(c) Semiconductor Components Industries, LLC, 2009
October, 2009 - Rev. 0
1
Publication Order Number: NTTFS4840N/D
NTTFS4840N
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter Junction-to-Case (Drain) Junction-to-Ambient - Steady State (Note 3) Junction-to-Ambient - Steady State (Note 4) Junction-to-Ambient - (t 10 s) (Note 3) 3. Surface-mounted on FR4 board using 1 sq-in pad, 1 oz Cu. 4. Surface-mounted on FR4 board using the minimum recommended pad size. Symbol RqJC RqJA RqJA RqJA Value 4.5 57.5 149.2 28.7 Unit C/W
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise specified)
Parameter OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage Drain-to-Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS/TJ IDSS IGSS VGS(TH) VGS(TH)/TJ RDS(on) ID = 20 A ID = 10 A ID = 20 A ID = 10 A VGS = 0 V, VDS = 24 V TJ = 25C TJ = 125C VGS = 0 V, ID = 250 mA 30 17 1.0 10 100 nA V mV/C mA Symbol Test Condition Min Typ Max Unit
Gate-to-Source Leakage Current ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain-to-Source On Resistance
VDS = 0 V, VGS = 20 V VGS = VDS, ID = 250 mA 1.5 5.6 15 15 28 25 22
3.0
V mV/C
VGS = 10 V to 11.5 V VGS = 4.5 V
24
mW
36
Forward Transconductance CHARGES AND CAPACITANCES Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate-to-Source Charge Gate-to-Drain Charge Total Gate Charge
gFS Ciss Coss Crss QG(TOT) QG(TH) QGS QGD QG(TOT) td(on) tr td(off) tf
VDS = 1.5 V, ID = 20 A
S
580 VGS = 0 V, f = 1.0 MHz, VDS = 15 V 140 80 5.5 VGS = 4.5 V, VDS = 15 V, ID = 20 A 0.75 2.2 2.8 VGS = 10 V, VDS = 15 V, ID = 20 A 10.8
pF
nC
nC
SWITCHING CHARACTERISTICS (Note 6) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time 10.5 VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W 38.2 11.5 2.6 ns
5. Pulse Test: pulse width = 300 ms, duty cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures.
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NTTFS4840N
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise specified)
Parameter Symbol Test Condition Min Typ Max Unit SWITCHING CHARACTERISTICS (Note 6) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time td(on) tr td(off) tf VSD tRR ta tb QRR LS LD LG RG TA = 25C VGS = 0 V, dIS/dt = 100 A/ms, IS = 20 A TJ = 25C TJ = 125C VGS = 10 V, VDS = 15 V, ID = 15 A, RG = 3.0 W 6.3 19.4 15.8 1.7 ns
DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VGS = 0 V, IS = 20 A 0.96 0.87 12.5 7.7 4.8 4.4 nC ns 1.2 V
Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge PACKAGE PARASITIC VALUES Source Inductance Drain Inductance Gate Inductance Gate Resistance
0.66 0.20 1.5 2.0 3.0
nH
W
5. Pulse Test: pulse width = 300 ms, duty cycle v 2%. 6. Switching characteristics are independent of operating junction temperatures.
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NTTFS4840N
TYPICAL CHARACTERISTICS
50 40 50 VDS 10 V ID, DRAIN CURRENT (A) 40 30 20 10 0 1.0 TJ = 25C
10 V
7.5 V TJ = 25C
VGS = 5 V 4.8 V 4.6 V
ID, DRAIN CURRENT (A)
30 20
4.4 V 4.2 V 4.0 V 3.8 V
10 0
3.6 V 3.4 V 3.3 V 3.0 V 3.5 4
TJ = 125C TJ = -55C 1.5 2.0 2.5 3.0 3.5 4.0 VGS, GATE-TO-SOURCE VOLTAGE (V)
0
0.5
1
1.5
2
2.5
3
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.050 ID = 20 A TJ = 25C 0.045 0.04 0.035 0.03 0.025 0.02 0.015 0.01 10
Figure 2. Transfer Characteristics
TJ = 25C
0.040
VGS = 4.5 V
0.030
0.020
VGS = 10 V
0.010
3
4
5
6
7
8
9
10
15
20 ID, DRAIN CURRENT (A)
25
30
VGS (V)
Figure 3. On-Resistance vs. VGS
1.7 1.6 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 -25 0 25 50 75 100 125 150 10 ID = 20 A VGS = 10 V IDSS, LEAKAGE (nA) 1000 10,000
Figure 4. On-Resistance vs. Drain Current and Gate Voltage
VGS = 0 V
TJ = 150C
100
TJ = 125C
5
10
15
20
25
30
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-to-Source Leakage Current vs. Voltage
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NTTFS4840N
TYPICAL CHARACTERISTICS
1000 900 C, CAPACITANCE (pF) 800 700 600 500 400 300 200 100 0 0 5 Crss 10 15 20 25 30 VDS, DRAIN-TO-SOURCE VOLTAGE (V) Coss Ciss VGS = 0 V TJ = 25C 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 TJ = 25C VDD = 15 V VGS = 10 V ID = 20 A 9 10 11 Qgs Qgd QT
VGS, GATE-TO-SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
100 IS, SOURCE CURRENT (A) VDD = 15 V ID = 15 A VGS = 10 V t, TIME (ns) td(off) tr tf 10 td(on) 20
Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge
15
10
5 VGS = 0 V TJ = 25C 0.5 0.6 0.7 0.8 0.9 1.0 1.1
1
1
10 RG, GATE RESISTANCE (W)
100
0 0.4
VSD, SOURCE-TO-DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation vs. Gate Resistance
EAS, SINGLE PULSE DRAIN-TO- SOURCE AVALANCHE ENERGY (mJ) 100 10 ms 100 ms 1 ms 1 VGS = 20 V Single Pulse TC = 25C RDS(on) Limit Thermal Limit Package Limit 1 10 10 ms 18 16 14 12 10 8 6 4 2 0 25
Figure 10. Diode Forward Voltage vs. Current
ID = 18.3 A
ID, DRAIN CURRENT (A)
10
0.1
dc
0.01 0.1
100
50
75
100
125
150
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature
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NTTFS4840N
TYPICAL CHARACTERISTICS
100 Duty Cycle = 50% 10 R(t) (C/W) 20% 10% 5% 1 2% 1% 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 PULSE TIME (sec) 0.1 1 10 100 1000
Figure 13. Thermal Response
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NTTFS4840N
PACKAGE DIMENSIONS
WDFN8 3.3x3.3, 0.65P CASE 511AB-01 ISSUE B
2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 2X
0.20 C D D1
8765
A
B
0.20 C E1 E
4X
q
1234
TOP VIEW 0.10 C A 0.10 C SIDE VIEW
8X b CAB
c
A1
6X
C
SEATING PLANE
e
DETAIL A
DETAIL A
DIM A A1 b c D D1 D2 E E1 E2 e G K L L1 M q
MILLIMETERS MIN NOM MAX 0.70 0.75 0.80 0.00 --- 0.05 0.23 0.30 0.40 0.15 0.20 0.25 3.30 BSC 2.95 3.05 3.15 1.98 2.11 2.24 3.30 BSC 2.95 3.05 3.15 1.47 1.60 1.73 0.65 BSC 0.30 0.41 0.51 0.64 --- --- 0.30 0.43 0.56 0.06 0.13 0.20 1.40 1.50 1.60 0_ --- 12 _
INCHES NOM 0.030 --- 0.012 0.008 0.130 BSC 0.116 0.120 0.078 0.083 0.130 BSC 0.116 0.120 0.058 0.063 0.026 BSC 0.012 0.016 0.025 --- 0.012 0.017 0.002 0.005 0.055 0.059 0_ --- MIN 0.028 0.000 0.009 0.006
MAX 0.031 0.002 0.016 0.010 0.124 0.088 0.124 0.068 0.020 --- 0.022 0.008 0.063 12 _
SOLDERING FOOTPRINT*
e/2
1 4
0.10 0.05
c
L
0.42 K
PACKAGE OUTLINE
8X
0.65 PITCH
0.66
4X
E2
8 5
M D2 BOTTOM VIEW L1 0.75 0.57 2.30 3.60
G
0.47
2.37 3.46
DIMENSION: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NTTFS4840N/D

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